In device scaling beyond the 5 nm semiconductor technology node, there is motivation for a gate all-around (GAA) device architecture. A basic requirement for GAA is the formation of silicon-germanium (SiGe) and silicon (Si) nanowires. Fabricating either Si or SiGe nanowires (also known as nanowire release) requires an extremely selective, isotropic and precise SiGe and Si etching, respectively. A continuous and sealed SiN liner is formed around the nanowire. This step is critical for the subsequent epitaxial growth required for source/drain formation.
Currently, as schematically shown in FIGS. 1A-1C and 2A-2C, in order to make SiGe nanowires, a Si/SiGe stack of alternating Si and SiGe layers is used. As schematically shown in FIGS. 3A-3C, the selectivity of Si etch with respect to SiGe (and vice versa) is often times not high enough to maintaining the desired profile of the SiGe nanowires/nanosheets that is needed to deposit the SiN liner. In addition, inadequate Si etch selectivity with respect to SiGe results in corner rounding of the nanowires. These imperfections from the etching cause further downstream issues with electrical performance, including capacitance and shorting problems between the gate and adjacent source/drain metals, and gate functionality.
FIGS. 1A-1C schematically show conventional fabrication of a n-type field effect transistor (NFET). In FIG. 1A, the method includes forming a film stack 1 containing alternating Si layers (101, 103) and SiGe layers (102, 104) on a substrate 100, and a SiN cap layer 110. In FIG. 1B, the method includes performing a selective etching process that recedes the SiGe layers (102, 104) relative to the Si layers (101, 103). In FIG. 1C, the method includes depositing a SiN liner 120 over the film stack 1, anisotropically removing portions of the SiN liner 120, and epitaxially growing source and drain regions 122 on the Si layers (101, 103) extending through the SiN liner 120. Thereafter, the SiGe layers (102, 104) may be removed from the film stack 1 by selective etching to form freestanding Si nanowires (not shown).
FIGS. 2A-2C schematically show conventional fabrication of a p-type field effect transistor (PFET). In FIG. 2A, the method includes forming a film stack 2 containing alternating Si layers (201, 203) and SiGe layers (202, 204) on a substrate 200, and a SiN cap layer 210. In FIG. 2B, the method includes performing a selective etching process that recedes the Si layers (201, 203) relative to the SiGe layers (202, 204). In FIG. 2C, the method includes depositing a SiN liner 220 over the film stack 2, anisotropically removing portions of the SiN liner 220, and epitaxially growing source and drain regions 222 on the SiGe layers (202, 204) extending through the SiN liner 220. Thereafter, the Si layers (201, 203) may be removed from the film stack 2 by selective etching to form freestanding Si nanowires (not shown).
FIGS. 3A-3C shows some of the problems encountered during conventional fabrication of a PFET. In FIG. 3A, the film stack 3 contains alternating Si layers (301, 303) and SiGe layers (302, 304) on a substrate 300, and a SiN cap layer 310. As schematically shown in FIG. 3B, poor Si: SiGe etch selectivity can form rounded layer edge fronts, which in turn can lead to improper epitaxial growth of source and drain regions 322 on the SiGe layers (302, 304), and formation of a non-uniform SiN liner 320 schematically shown in FIG. 3C.
In the above described integration or process sequence, one of the major challenge is formation of the nanowires. In particular, the etch selectivity required to form the nanowires is often inadequate. In addition, the etching process also has to be isotropic in high aspect ratio structures. Such limitations and requirements require new novel integration and etch processes.